Electrolytic gold plating method of printed circuit board

ABSTRACT

Disclosed is an electrolytic gold plating method of a PCB, which includes (A) forming an electrolytic copper-plated layer, corresponding to a predetermined copper plating resist pattern, on a substrate, (B) forming an electrolytic gold-plated layer, corresponding to a predetermined gold plating resist pattern, on the substrate using an outer layer of the substrate as a first incoming line for electrolytic gold plating use, and (C) removing a portion of the outer layer of the substrate, on which the electrolytic copper-plated layer is not coated.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention pertains, in general, to an electrolytic goldplating method of a printed circuit board (PCB) and, in particular, toan electrolytic gold plating method of a PCB, in which a copper outerlayer or an electroless copper-plated layer of a substrate is used as anincoming line for plating use to form an electrolytic gold-plated layer.

2. Description of the Prior Art

Generally, a process of mounting passive components, active integratedcircuits, and the like on a PCB according to a wire bonding manner isclassified into an electrolytic gold plating process and an electrolessgold plating process.

In this regard, the electroless gold plating process has a disadvantageof a separation occurring at an interface between copper and nickelduring a wire bonding process of the PCB, and thus, the electrolyticgold plating process is more frequently used than the electroless goldplating process. Unlike other processes of surface-treating the PCBwithout using electricity, the electrolytic gold plating process isadvantageous in that an electrolytic gold-plated layer is thick, theproductivity is relatively high, and a relatively high peel strengthreliability is secured.

The electrolytic gold plating process may be classified into anelectrolytic soft gold plating process and an electrolytic hard goldplating process. In this respect, the electrolytic soft gold platingprocess is applied to the wire bonding process of typical semiconductorpackage products because gold particles plated on the PCB are relativelylarge, porous, and have a relatively low density. On the other hand, theelectrolytic hard gold plating process is applied to produce a contactterminal for a battery of a mobile phone because the gold particlesplated on the PCB are densely arranged, and have a relatively highdensity and excellent strength.

In order to better understand the background of the present invention, adescription will be given of the production of a conventional PCB,below.

FIGS. 1 a to 1 k are sectional views illustrating the production of theconventional PCB, and FIG. 2 is a plan view of the conventional PCBproduced according to a procedure of FIGS. 1 a to 1 k. At this time,FIGS. 1 a to 1 k are the sectional views taken along the line a-a′ ofFIG. 2.

With reference to FIG. 1 a, upper and lower copper foil layers 11 b arecoated on upper and lower sides of an insulating resin layer 11 a toproduce a copper clad laminate 11.

Referring to FIG. 1 b, a via hole (b) is formed through the copper cladlaminate 11 to electrically connect the upper and lower copper foillayers 11 b to each other.

In FIG. 1 c, an electroless copper plating process is conducted to allowan electric current to flow through the via hole (b), thereby forming anelectroless copper-plated layer 12 on the upper and lower copper foillayers 11 b and a wall of the via hole (b).

Subsequently, an electrolytic copper plating process is conducted toform an electrolytic copper-plated layer 13 on the electrolesscopper-plated layer 12 plated on the upper and lower copper foil layers11 b and the wall of the via hole (b) as shown in FIG. 1 d. At thistime, the electrolytic copper-plated layer 13 has excellent physicalproperties.

Coated on the electrolytic copper-plated layer 13, a dry film 20 isexposed and developed using a first artwork film, having a predeterminedpattern printed thereon, to be patterned as shown in FIG. 1 e. Thepattern of the first artwork film may be exemplified by a circuitpattern, a land of the via hole (b), a wire bonding terminal pattern,and an incoming line pattern.

In FIG. 1 f, the resulting copper clad laminate 11 is dipped in anetching solution to remove a portion of the upper and lower copper foillayers 11 b, electroless copper-plated layer 12, and electrolyticcopper-plated layer 13, which is not coated with the patterned dry film20. At this time, the patterned dry film 20 acts as an etching resist.

The dry film 20 coated on the patterned copper clad laminate 11 is thenremoved as shown in FIG. 1 g.

Subsequently, a solder resist 14 is coated on the patterned copper cladlaminate 11, and preliminarily dried as shown in FIG. 1 h.

Referring to FIG. 1 i, a second artwork film 30, having a solder resistpattern printed thereon, is mounted on the solder resist 14 coated onthe patterned copper clad laminate 11, exposed, and developed to cure aportion of the solder resist 14 corresponding in position to the solderresist pattern of the second artwork film 30.

After the second artwork film 30 is removed from the patterned copperclad laminate 11, a uncured portion of the solder resist 14 is removedfrom the patterned copper clad laminate 11 to construct the solderresist pattern on the patterned copper clad laminate 11 as shown in FIG.1 j.

In FIG. 1 k, a wire bonding terminal, that is, an opening (c) of thesolder resist pattern on the patterned copper clad laminate 11 issubjected to an electrolytic gold plating process to form theelectrolytic gold-plated layer 15 on the patterned copper clad laminate11.

Subsequently, an outer structure of the patterned copper clad laminate11 is formed using a router or a power press to accomplish the PCB 10 asshown in FIG. 2.

Conventionally, regardless of the circuit pattern, incoming lines 16 forplating use had to be formed on the PCB 10 to form the electrolyticgold-plated layer 15 as shown in the dotted ellipse of FIG. 2.

With respect to this, the incoming lines 16 are mostly removed in thecourse of forming the outer structure of the copper clad laminate 11using the router or power press, but a small portion of the incominglines 16 remains on the PCB 10. Sometimes, a large portion of theincoming lines 16 may not be removed but remain on the PCB 10 accordingto a method of designing the PCB 10.

In accordance with the recent trend of a functional improvement and aminiaturization of electronic products, demand for highly fine andintegrated circuit patterns of the PCB 10 are increasing. However, theincoming lines 16 remaining on the PCB 10 have no relation to thecircuit pattern, thus limiting the degree of freedom in designing thePCB 10.

As well, the incoming lines 16 remaining on the PCB 10 act as aconductor in a relatively high frequency environment caused by anincreased data communication speed. Accordingly, the incoming lines 16act as a sort of antenna to bring about a parasitic inductance.

The parasitic inductance interferes with the electric signals of thecircuit pattern to cause an impedance mismatching, which reduces theperformances of the electronic products.

Furthermore, a signal to noise ratio of each electronic product isreduced due to the parasitic inductance, leading to the misoperation ofthe electronic product to reduce the reliability of the electronicproduct.

SUMMARY OF THE INVENTION

Therefore, the present invention has been made keeping in mind the abovedisadvantages occurring in the prior arts, and an object of the presentinvention is to provide an electrolytic gold plating method of a PCBwithout using a separate incoming line for plating use.

The above object can be accomplished by providing an electrolytic goldplating method of a printed circuit board, which includes (A) forming anelectrolytic copper-plated layer, corresponding to a predeterminedcopper plating resist pattern, on a substrate, (B) forming anelectrolytic gold-plated layer, corresponding to a predetermined goldplating resist pattern, on the substrate using an outer layer of thesubstrate as a first incoming line for electrolytic gold plating use,and (C) removing a portion of the outer layer of the substrate, on whichthe electrolytic copper-plated layer is not coated.

The electrolytic gold plating method may also include (D) forming a viahole through the substrate, and (E) forming an electroless copper-platedlayer on the outer layer of the substrate and on a wall of the via hole,prior to the step of (A). At this time, the electroless copper-platedlayer is used as the first incoming line in the step of (B).

Additionally, the step of (A) includes (A-1) coating a copper platingresist on the electroless copper-plated layer of the substrate, andexposing and developing the copper plating resist to form apredetermined copper plating resist pattern on the electrolesscopper-plated layer, (A-2) conducting an electrolytic copper platingprocess, using the outer layer and electroless copper-plated layer ofthe substrate as a second incoming line for electrolytic copper platinguse, to form an electrolytic copper-plated layer, corresponding to thecopper plating resist pattern, on the electroless copper-plated layer ofthe substrate, and (A-3) removing the copper plating resist.

The electrolytic gold plating method may also include (D) processing theouter layer of the substrate to be thin, prior to the step of (A).

In this regard, the copper plating resist includes a photosensitivematerial.

Further, the step of (B) includes (B-1) coating a gold plating resist onthe electroless copper-plated layer of the substrate, and exposing anddeveloping the gold plating resist to form a predetermined gold platingresist pattern on the electroless copper-plated layer, (B-2) conductingan electrolytic gold plating process, using the outer layer andelectroless copper-plated layer of the substrate as the first incomingline, to form an electrolytic gold-plated layer, corresponding to thegold plating resist pattern, on the electroless copper-plated layer ofthe substrate, and (B-3) removing the gold plating resist.

The electrolytic gold plating method may also include (B-4) conductingan electrolytic nickel plating process, using the electrolesscopper-plated layer as a third incoming line for electrolytic nickelplating use, to form an electrolytic nickel-plated layer, correspondingto the gold plating resist pattern, on the electroless copper-platedlayer of the substrate after the step of (B-1).

In this respect, the gold plating resist includes a photosensitivematerial.

Furthermore, the substrate is dipped in an etching solution capable ofetching copper, but not gold, to remove a portion of the electrolesscopper-plated layer and the outer layer of the substrate, which is notcoated with the electrolytic copper-plated layer, in the step of (C). Atthis time, the outer layer of the substrate is in contact with theelectroless copper-plated layer.

As well, the step of (C) includes (C-1) coating an etching resist on theelectroless copper-plated layer of the substrate, and exposing anddeveloping the etching resist to form a predetermined etching resistpattern, which is not coated with the electrolytic copper-plated layer,on the electroless copper-plated layer of the substrate, (C-2) etching aportion of the electroless copper-plated layer and outer layer of thesubstrate, which is not coated with the etching resist pattern, and(C-3) removing the etching resist. At this time, the outer layer is incontact with the electroless copper-plated layer.

Furthermore, the etching resist includes a photosensitive material.

In addition, the substrate is dipped in an etching solution to remove aportion of the electroless copper-plated layer and the outer layer ofthe substrate, which is not coated with the electrolytic copper-platedlayer, in the step of (C-2). At this time, the outer layer of thesubstrate is in contact with the electroless copper-plated layer.

Furthermore, a portion of the electroless copper-plated layer and theouter layer of the substrate, which is not coated with the electrolyticcopper-plated layer, is etched through a plasma etching process in thestep of (C-2). At this time, the outer layer of the substrate is incontact with the electroless copper-plated layer.

The electrolytic gold plating method may also include (D) coating asolder resist on a patterned substrate to form a predetermined solderresist pattern on the patterned substrate after the step of (C).

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other objects, features and other advantages of thepresent invention will be more clearly understood from the followingdetailed description taken in conjunction with the accompanyingdrawings, in which:

FIGS. 1 a to 1 k are sectional views illustrating the production of aconventional PCB;

FIG. 2 is a plan view of the conventional PCB produced according to aprocedure of FIGS. 1 a to 1K;

FIGS. 3 a to 3 k are sectional views illustrating the production of aPCB according to the first embodiment of the present invention;

FIG. 4 is a plan view of the PCB produced according to a procedure ofFIGS. 3 a to 3 k; and

FIG. 5 is a plan view of a PCB according to the second embodiment of thepresent invention.

DETAILED DESCRIPTION OF THE INVENTION

Reference now should be made to the drawings, in which the samereference numerals are used throughout the different drawings todesignate the same or similar components.

FIGS. 3 a to 3 k are sectional views illustrating the production of aPCB according to the first embodiment of the present invention, and FIG.4 is a plan view of the PCB produced according to a procedure of FIGS. 3a to 3 k. At this time, FIGS. 3 a to 3 k are sectional views taken alongthe line A-A′ of FIG. 4.

With reference to FIG. 3 a, copper foil layers 112 are coated on bothsides of an insulating resin layer 111 to fabricate a substrate 110,that is, a copper clad laminate. At this time, it is preferable that thecopper foil layers 112 be thinly coated on the insulating resin layer111 in consideration of the fact that the copper foil layers 112 areetched and removed in subsequent processes.

Examples of the copper clad laminate used as the substrate 110 mayinclude a glass/epoxy copper clad laminate, a heat-resistant resincopper clad laminate, a paper/phenol copper clad laminate, a highfrequency copper clad laminate, a flexible copper clad laminate, and acomplex copper clad laminate. Preferably, the glass/epoxy copper cladlaminate, in which the copper foil layers 112 are coated on both sidesof the insulating resin layer 111, is used to fabricate a double-sidedPCB or a multilayer PCB.

Referring to FIG. 3 b, a via hole (B) is formed through the copper cladlaminate to electrically connect upper and lower copper foil layers 112to each other.

In this regard, the via hole (B) is formed at a predetermined positionof the copper clad laminate using a computer numerical control drill(CNC drill) or a laser beam.

The CNC drill is useful to form the via hole (B) through thedouble-sided PCB or to form a through hole through the multilayer PCB.After the via hole (B) or through hole is formed using the CNC drill, adeburring process is conducted to remove burrs of a copper foilgenerated in the course of drilling the copper clad laminate, and dustattached to a wall of the via hole (B) and to surfaces of the copperfoil layers 112. At this time, the surfaces of the copper foil layers112 become rough, thus improving an attachment force of copper to thecopper foil layers 112 in a copper plating process.

The laser beam is useful to form a micro via hole through the multilayerPCB. For example, the copper foil layers 112 and the insulating resinlayer 111 may be simultaneously holed by a yttrium aluminum garnet (YAG)laser beam, or the insulating resin layer 111 may be holed by a carbondioxide laser beam after a portion of each copper foil layer 112corresponding in position to the via hole is etched.

Meanwhile, a portion of the insulating resin layer 111 of the substrate110 may be molten due to heat generated in the course of forming the viahole (B) to form a smear on the wall of the via hole (B). Accordingly,it is preferable that a desmear process be conducted after the via hole(B) is formed through the copper clad laminate so as to remove the smearon the wall of the via hole (B).

In FIG. 3 c, an electroless copper plating process is conducted to forman electroless copper-plated layer 120 on the upper and lower copperfoil layers 112 and wall of the via hole (B) of the substrate 110.

In this respect, the wall of the via hole (B) of the substrate 110 iscomprised of the insulating resin layer 111, and thus, it is impossibleto conduct an electrolytic copper plating process directly after the viahole (B) is formed through the copper clad laminate. Accordingly, theelectroless copper plating process is conducted prior to conducting theelectrolytic copper plating process to electrically connect the upperand lower copper foil layers 112 to each other through the via hole (B).In the electroless copper plating process, the insulating resin layer111 is plated by copper without the actions of ions with electricity. Inother words, the electroless copper plating process is achieved by thedeposition of copper on the copper foil layers 112, and the depositionof copper is promoted by a catalyst. In detail, the catalyst is attachedto the surface of each copper foil layer 112 so as to separate copperfrom a plating solution to deposit copper on the copper foil layer 112.Hence, the electroless copper plating process requires some pre-treatingprocesses.

For example, the electroless copper plating process may include adegreasing step, a soft etching step, a pre-catalyst treating step, acatalyst treating step, an accelerator step, an electroless copperplating step, and an anti-oxidizing step.

In the degreasing step, oxides, impurities, oils and fats are removedfrom the surfaces of the copper foil layers 112 using a solutioncontaining acid or alkaline surfactants, and the resulting copper foillayers 112 are rinsed to remove the solution therefrom.

The soft etching step makes the surfaces of the copper foil layers 112slightly rough (for example, a roughness of about 1-2 μm) to uniformlydeposit copper particles on the copper foil layers 112 and to removecontaminants, which are not removed in the degreasing step, from thecopper foil layers 112.

In the pre-catalyst treating step, the substrate 110 is dipped in adilute first catalyst-containing chemical to prevent a secondcatalyst-containing chemical used in the catalyst treating step frombeing contaminated by the impurities attached to the substrate 110 or toprevent a concentration of the second catalyst-containing chemical frombeing changed due to the contaminants attached to the substrate 110.Moreover, because the substrate 110 is preliminarily dipped in the firstchemical, having the same components as the second chemical, prior totreat the substrate 110 using the second chemical, the treating of thesubstrate 110 using the catalyst is more preferably achieved. At thistime, it is preferable that 1-3% chemical be used in the pre-catalysttreating step.

In the catalyst treating step, catalyst powder is coated on the copperfoil layers 112 and insulating resin layer 111 (the wall of the via hole(B)) of the substrate 110. In this respect, the catalyst powder may beexemplified by Pd—Sn compound powder, and Pd₂ ⁻ dissociated from thePd—Sn compound powder contributes to promoting the plating of thesubstrate 110 in conjunction with Cu₂ ⁺ plated on the substrate 110.

During the electroless copper plating step, it is preferable that theplating solution contain CuSO₄, HCHO, NaOH, and a stabilizer. At thistime, it is important to control a composition of the plating solutionbecause chemical reactions constituting the plating process of thesubstrate 110 must maintain an equilibrium state in order to desirablyconduct the plating process. Accordingly, it is necessary to properlyreplenish each component constituting the plating solution, mechanicallyagitate the plating solution, and smoothly operate a cycling system ofthe plating solution so as to desirably maintain the composition of theplating solution. Furthermore, it is necessary to use a filtering deviceto remove by-products, and the removal of the byproducts using thefiltering device contributes to extending a life of the platingsolution.

An anti-oxidizing layer is coated on the substrate 110 to prevent copperfrom being oxidized due to alkaline components remaining on the copperclad laminate after the electroless copper plating step in theanti-oxidizing step.

However, the electroless copper-plated layer 120 has poorer physicalproperties than an electrolytic copper-plated layer. Therefore, it ispreferable to thinly form the electroless copper-plated layer 120 on thesubstrate 110.

Referring to FIG. 3 d, a dry film 200 is coated on the electrolesscopper-plated layer 120, exposed and developed using an artwork film,having a predetermined pattern printed thereon, to be patterned. Thepattern of the artwork film 200 may be exemplified by a circuit pattern,a land of the via hole (B), and a wire bonding terminal pattern.

The dry film 200 includes three films: a cover film, a photoresist film,and a Mylar film. Of the three films, the photoresist film substantiallyacts as a resist layer against ultraviolet light.

After the artwork film with the predetermined pattern is mounted on thedry film 200, the ultraviolet light is irradiated to the artwork film toexpose and develop the dry film 200. At this time, the ultraviolet lightis not transmitted through a black portion of the artwork film, whichcorresponds to the pattern, but through a remaining portion of theartwork film, on which the pattern is not printed, to cure the dry film200 under the artwork film. The copper clad laminate on which the cureddry film 200 is mounted is dipped in a developing solution to remove anuncured portion of the dry film 200. In this regard, a remaining curedportion of the dry film 200 forms a resist pattern. With respect tothis, examples of the developing solution include a sodium carbonate(Na₂CO₃) aqueous solution and a potassium carbonate (K₂CO₃) aqueoussolution.

With reference to FIG. 3 e, the substrate 110 on which the patterned dryfilm 200 is mounted is subjected to the electrolytic copper platingprocess to form the electrolytic copper-plated layer 130 on theelectroless copper-plated layer 120 formed on the upper and lower copperfoil layers 112 and wall of the via hole (B). In this regard, thepatterned dry film 200 is used as a plating resist, and the upper andlower copper foil layers 112 of the substrate 110 are used as incominglines for an electrolytic copper plating process.

At this time, the substrate 110 having the patterned dry film 200mounted thereon is dipped in the plating solution in a vessel, andsubjected to the electrolytic copper plating process using a DCrectifier (direct current rectifier). In this respect, a proper amountof electricity is applied by the DC rectifier to the substrate 110 basedon a calculated area of the substrate 110, which is to be plated withcopper, thereby depositing copper on the substrate 110 having thepatterned dry film 200 mounted thereon.

The electrolytic copper-plated layer 130 has superior physicalproperties to the electroless copper-plated layer 120, and it is easy toform the relatively thick electrolytic copper-plated layer 130 on theelectroless copper-plated layer 120.

After the completion of the electrolytic copper plating process, the dryfilm 200 is removed from the substrate 110 as shown in FIG. 3 f.

In this respect, a delaminating solution, such as sodium hydroxide(NaOH) and potassium hydroxide (KOH), is used to remove the dry film 200from the substrate 110.

In FIGS. 3 d to 3 f, the dry film 200 is used as the plating resist, buta photosensitive liquid may be alternatively used as the plating resist.In the case of using the photosensitive liquid as the plating resist,the photosensitive liquid, which is to be exposed to the ultravioletlight, is coated on the electroless copper plated-layer 120 plated onthe substrate 110, and then dried to form a photosensitive layer on theelectroless copper-plated layer 120. Subsequently, the photosensitivelayer is exposed and developed by the ultraviolet light using thepatterned artwork film 300 to be patterned. In this respect, thepatterned photosensitive layer acts as the plating resist. The substrate110 having the patterned photosensitive layer mounted thereon is thendipped in the plating solution in the vessel, and subjected to theelectrolytic copper plating process using the DC rectifier to form theelectrolytic copper-plated layer 130 on the electroless copper-platedlayer 120 plated on the upper and lower copper foil layers 112 and thewall of the via hole (B) of the substrate 110. After the completion ofthe electrolytic copper plating process, the photosensitive layer isremoved from the substrate 110. Examples of a process of coating thephotosensitive liquid on the substrate 110 include a dip coatingprocess, a roll coating process, and an electro-depositing process.

Referring to FIG. 3 g, after a gold plating resist 300 is coated on theelectrolytic copper-plated layer 130, the gold plating resist 300 isexposed and developed using an artwork film, having an electrolytic goldplating pattern printed thereon, to be patterned.

The substrate 110 is then subjected to an electrolytic gold platingprocess using the patterned gold plating resist 300 to form anelectrolytic gold-plated layer 150 on the electrolytic copper-platedlayer 130 of the substrate 110 as shown in FIG. 3 h. Like in the case ofthe electrolytic copper plating process in FIG. 3 e, the electrolyticgold plating process is conducted using the copper foil layers 112 asthe incoming lines, and thus, it is not necessary to form a separateincoming line in the electrolytic gold plating process.

Subsequently, the substrate 110 having the electrolytic gold-platedlayer 150 mounted thereon is dipped in the plating solution in thevessel, and then subjected to the electrolytic gold plating processusing the DC rectifier. At this time, a proper intensity of electricityis applied by the DC rectifier to the substrate 110 based on acalculated area of the substrate 110, which is to be plated with gold,thereby depositing gold on the electrolytic copper-plated layer 130 ofthe substrate 110.

Additionally, the electrolytic gold plating process may be conductedafter nickel is thinly coated on the electrolytic copper-plated layer130 so as to increase an attachment force of gold to the electrolyticcopper-plated layer 130.

Subsequently, the gold plating resist 300 is removed from the substrate110 as shown in FIG. 3 i.

The gold plating resist 300 used in FIGS. 3 g to 3 i may be the dry film200 or photosensitive liquid in FIGS. 3 d to 3 f.

With reference to FIG. 3 j, a portion of the electroless copper-platedlayer 120 and copper foil layers 112, which is not coated with theelectrolytic copper-plated layer 130, is removed from the substrate 110to pattern the copper clad laminate. At this time, the pattern of thecopper clad laminate includes the circuit pattern, the land of the viahole (B), and the wire bonding terminal pattern.

With respect to this, the removal of the electroless copper-plated layer120 and copper foil layers 112 from the substrate 110 may be conductedaccording to various processes.

In detail, according to one process, the substrate 110 is dipped in anetching solution capable of etching the electroless copper-plated layer120 and copper foil layers 112 but not the electrolytic gold-platedlayer 150. At this time, a portion of the electroless copper-platedlayer 120 and copper foil layers 112 is easily removed from thesubstrate 110 because pre-treating processes are conducted so as to makethe copper foil layers 112 thin in FIG. 3 a and the electrolesscopper-plated layer 120 is thinly formed on the substrate 110. However,the circuit pattern, the land and wall of the via hole (B), or wirebonding terminal pattern include the thick electrolytic copper-platedlayer 130 with excellent physical properties as well as the copper foillayers 112 and electroless copper-plated layer 120. Accordingly, thecopper foil layers 112 and electroless and electrolytic copper-platedlayers 120, 130 are insufficiently etched.

According to another process, an etching resist, such as the dry film200, is coated on the electroless copper-plated layer 120 of thesubstrate 110, and is patterned so as to protect the circuit pattern,the land of the via hole (B), or the wire bonding terminal pattern. Theresulting substrate 110 is then dipped in the etching solution to removea useless portion of the electroless copper-plated layer 120 and copperfoil layers 112.

According to the third process, the etching resist, such as the dry film200, is coated on the electroless copper-plated layer 120 of thesubstrate 110, and is patterned so as to protect the circuit pattern,the land of the via hole (B), or the wire bonding terminal pattern.Subsequently, a useless portion of the electroless copper-plated layer120 and copper foil layers 112 of the substrate 110 is removed accordingto a plasma etching process. In this respect, a side wall of the circuitpattern is precisely processed due to an anisotropic etching consideredas an advantage of the plasma etching process.

Referring to FIG. 3 k, a solder resist 140 is coated on the patternedsubstrate 110, and then patterned to form a solder resist pattern on thepatterned substrate 110.

A detailed description will be given of the formation of the solderresist pattern, below. The solder resist 140 is coated on the patternedsubstrate 110 and then preliminarily dried. At this time, examples of aprocess of coating the solder resist 140 on the patterned substrate 110include a screen printing process, a roller coating process, a curtaincoating process, and a spray coating process.

Subsequently, an artwork film having the solder resist pattern printedthereon is mounted on the patterned substrate 110, exposed, anddeveloped to cure a portion of the solder resist 140 corresponding inposition to the solder resist pattern. The artwork film and an uncuredportion of the solder resist 140 are sequentially removed to form thesolder resist pattern on the patterned substrate 110. The primarilycured solder resist 140 is completely cured by the ultraviolet light anda drier, and a residue of the solder resist 140, which is to be removed,and impurities are removed by a plasma.

An exterior structure of the copper clad laminate is then constructedusing the router or the power press to accomplish the PCB 100 as shownin FIG. 4.

With reference to FIG. 4, the PCB 100 according to the present inventionhas no incoming lines as shown in a dotted ellipse. The reason for thisis that the electroless copper-plated layer 120 is used as the incomingline for the electrolytic gold plating process and removed from thesubstrate 110 after the completion of the electrolytic gold platingprocess.

As described above, FIGS. 3 and 4 illustrate the double-sided PCB, whichis fabricated using the copper clad laminate as the substrate 110.However, a single-sided PCB or a multilayer PCB may be fabricatedaccording to the electrolytic gold plating process without using theincoming line, if necessary.

In the case of fabricating the multilayer PCB, a pattern including aground circuit and a signal process circuit is formed on an inner layerof the multilayer PCB. At this time, a copper foil is attached to theinner layer using an insulator adhesive resin, such as prepreg, or resincoated copper (RCC) is laminated on the inner layer to form an outerlayer. The outer layer is then subjected to the electrolytic goldplating process as shown in FIGS. 3 a to 3 k to accomplish themultilayer PCB.

FIG. 5 is a plan view of a PCB according to the second embodiment of thepresent invention.

As shown in FIG. 5, the PCB 100 according to the present invention isadvantageous in that the circuit pattern may be additionally formedinstead of the incoming line on a portion of the PCB corresponding to adotted ellipse of FIG. 5 because it is not necessary to form theincoming line in the course of designing the PCB. Therefore, the degreeof freedom is increased in the course of designing the PCB, therebyhighly integrating the circuit pattern on the PCB 100′.

The present invention has been described in an illustrative manner, andit is to be understood that the terminology used is intended to be inthe nature of description rather than of limitation. Many modificationsand variations of the present invention are possible in light of theabove teachings. Therefore, it is to be understood that within the scopeof the appended claims, the invention may be practiced otherwise than asspecifically described.

As apparent from the above description, the present invention providesan electrolytic gold plating method of a PCB without using an incomingline for plating use.

Therefore, the electrolytic gold plating method according to the presentinvention is advantageous in that a circuit pattern is formed instead ofthe incoming line on a portion of the PCB, on which the incoming linewas positioned conventionally, thereby improving the degree of freedomin the course of designing the PCB.

Another advantage of the electrolytic gold plating method according tothe present invention is that a parasitic inductance caused by theincoming line does not occur because the PCB of the present inventionhas no incoming line.

Furthermore, the PCB according to the present invention has no incomingline, and thus, the parasitic inductance does not occur, a signal tonoise ratio of an electronic product, fabricated using the PCB of thepresent invention, is improved in a relatively high frequencyenvironment, an impedance matching is easily accomplished, a suddenmisoperation of the electronic product is prevented, and electricperformances and reliability of the PCB are improved.

1. An electrolytic gold plating method of a printed circuit board,comprising: (A) forming an electrolytic copper-plated layer,corresponding to a predetermined copper plating resist pattern, on asubstrate; (B) forming an electrolytic gold-plated layer, correspondingto a predetermined gold plating resist pattern, on the substrate usingan outer layer of the substrate as a first incoming line forelectrolytic gold plating use; and (C) removing a portion of the outerlayer of the substrate, on which the electrolytic copper-plated layer isnot coated.
 2. The electrolytic gold plating method as set forth inclaim 1, further comprising: (D) forming a via hole through thesubstrate; and (E) forming an electroless copper-plated layer on theouter layer of the substrate and on a wall of the via hole, prior to thestep of (A), the electroless copper-plated layer being used as the firstincoming line in the step of (B).
 3. The electrolytic gold platingmethod as set forth in claim 2, wherein the step of (A) comprises: (A-1)coating a copper plating resist on the electroless copper-plated layerof the substrate, and exposing and developing the copper plating resistto form a predetermined copper plating resist pattern on the electrolesscopper-plated layer; (A-2) conducting an electrolytic copper platingprocess, using the outer layer and electroless copper-plated layer ofthe substrate as a second incoming line for electrolytic copper platinguse, to form an electrolytic copper-plated layer, corresponding to thecopper plating resist pattern, on the electroless copper-plated layer ofthe substrate; and (A-3) removing the copper plating resist.
 4. Theelectrolytic gold plating method as set forth in claim 2, furthercomprising: (D) processing the outer layer of the substrate to be thin,prior to the step of (A).
 5. The electrolytic gold plating method as setforth in claim 3, wherein the copper plating resist includes aphotosensitive material.
 6. The electrolytic gold plating method as setforth in claim 2, wherein the step of (B) comprises: (B-1) coating agold plating resist on the electroless copper-plated layer of thesubstrate, and exposing and developing the gold plating resist to form apredetermined gold plating resist pattern on the electrolesscopper-plated layer; (B-2) conducting an electrolytic gold platingprocess, using the outer layer and electroless copper-plated layer ofthe substrate as the first incoming line, to form an electrolyticgold-plated layer, corresponding to the gold plating resist pattern, onthe electroless copper-plated layer of the substrate; and (B-3) removingthe gold plating resist.
 7. The electrolytic gold plating method as setforth in claim 6, further comprising (B-4) conducting an electrolyticnickel plating process, using the electroless copper-plated layer as athird incoming line for electrolytic nickel plating use, to form anelectrolytic nickel-plated layer, corresponding to the gold platingresist pattern, on the electroless copper-plated layer of the substrateafter the step of (B-1).
 8. The electrolytic gold plating method as setforth in claim 6, wherein the gold plating resist includes aphotosensitive material.
 9. The electrolytic gold plating method as setforth in claim 2, wherein the substrate is dipped in an etching solutioncapable of etching copper, but not gold, to remove a portion of theelectroless copper-plated layer and the outer layer of the substrate,which is not coated with the electrolytic copper-plated layer, in thestep of (C), the outer layer of the substrate being in contact with theelectroless copper-plated layer.
 10. The electrolytic gold platingmethod as set forth in claim 2, wherein the step of (C) comprises: (C-1)coating an etching resist on the electroless copper-plated layer of thesubstrate, and exposing and developing the etching resist to form apredetermined etching resist pattern, which is not coated with theelectrolytic copper-plated layer, on the electroless copper-plated layerof the substrate; (C-2) etching a portion of the electrolesscopper-plated layer and outer layer of the substrate, which is notcoated with the etching resist pattern, the outer layer being in contactwith the electroless copper-plated layer; and (C-3) removing the etchingresist.
 11. The electrolytic gold plating method as set forth in claim10, wherein the etching resist includes a photosensitive material. 12.The electrolytic gold plating method as set forth in claim 10, whereinthe substrate is dipped in an etching solution to remove a portion ofthe electroless copper-plated layer and the outer layer of thesubstrate, which is not coated with the electrolytic copper-platedlayer, in the step of (C-2), the outer layer of the substrate being incontact with the electroless copper-plated layer.
 13. The electrolyticgold plating method as set forth in claim 10, wherein a portion of theelectroless copper-plated layer and the outer layer of the substrate,which is not coated with the electrolytic copper-plated layer, is etchedthrough a plasma etching process in the step of (C-2), the outer layerof the substrate being in contact with the electroless copper-platedlayer.
 14. The electrolytic gold plating method as set forth in claim 2,further comprising (D) coating a solder resist on a patterned substrateto form a predetermined solder resist pattern on the patterned substrateafter the step of (C).